Design and method for semi-conducting devices with enhanced conductivity and performance
This technology can be applied to various electrical devices such as metal–oxide–semiconductor field-effect transistors (MOSFETs).
There is need for higher currents in MOSFETs.
This invention consists of a tri-channel hetero-structure which has a tensile strained semiconductor layer, a compressively strained layer and a confining layer. The thicknesses and doping concentrations of the first two layers are optimized for wide ranges of performance enhancement. The third layer has a band offset with the second layer to confine carriers, and provides a diffusion barrier to the second layer over a large temperature range. A gate dielectric could be disposed over the first, the second or the third layer to form a MOSFET. A method of forming the above structure is also provided.
- High hole and electron mobilities
- High performance over a large processing temperature range