Waveguide Formation through Post-foundry Processing using Patterned Shallow Trench Isolation of CMOS Die

Technology #16489

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Professor Rajeev Ram
Research Laboratory for Electronics, MIT
External Link (www.rle.mit.edu)
Jason Orcutt
Research Laboratory for Electronics, MIT
External Link (www.rle.mit.edu)
Karan Mehta
Research Laboratory for Electronics, MIT
External Link (www.rle.mit.edu)
Amir Atabaki
Research Laboratory for Electronics, MIT
Managed By
Jim Freedman
MIT Technology Licensing Officer - Chemicals, Instruments, Consumer Products
Patent Protection

Waveguide formation using cmos fabrication techniques

US Patent Pending US 2017-0146740

Waveguide formation using CMOS fabrication techniques

US Patent 9,529,150
Silicon Photonics Meets the Foundry
ILP News, June 22nd, 2015

The technology uses in-foundry formed shallow trench isolation layers as the high-resolution patterning template to form integrated waveguide features for electronic-photonic integrated devices.


  • Communication transceivers
  • Application specific integrated circuits requiring electronic-photonic integration
  • Integrated quantum optics
  • Integrated photonic biosensing
  • Optical I/O

Problem Addressed

Optical I/O resolves one of the major bottlenecks in inter and intra chip communications. However, creating waveguides for photonic-electronic devices in bulk semiconductor manufacturing process requires complicated post-processing and high-resolution lithography, which is very costly. Alternatively, back-end integrated waveguides are physically distant from the transistor body layer, making integration with silicon photodetectors, etc., difficult. Deposited dielectric layers also reduce the thermal conductance of the entire chip, reducing allowable power dissipation and hindering performance.


The invention utilizes shallow trench isolation features patterned during in-foundry processing for subsequent waveguide formation via a post-process dielectric deposition. This is accomplished after etching the silicon on the back side of the wafer and then exposing the photonic integration region, where the desired photonic waveguide core dielectric layer is uniformly deposited, and finally depositing a lower cladding dielectric layer on the waveguide cores. This process is entirely CMOS compatible and utilizes standard patterning and etching techniques.


  • Low-loss, high patterning resolution waveguide within electronics process utilizing bulk starting wafers
  • Waveguide in-plane with transistor body layer allows coupling to other electronic/photonic devices
  • Standard CMOS process flow
  • Improved waveguide integration for wavelengths covering 400nm – 1150 nm with arbitrary dielectrics
  • Reduced dielectric covering of die or wafer, which increases total allowable power dissipation