Detecting Timing-Skew in Time-Interleaved ADCs As a Background Task

Technology #16854

Questions about this technology? Ask a Technology Manager

Download Printable PDF

Professor Anantha Chandrakasan
Department of Electrical Engineering-Computer Science, MIT
External Link (
Hae-Seung Lee
Department of Electrical Engineering-Computer Science, MIT
Sunghyuk Lee
Department of Electrical Engineering-Computer Science, MIT
Managed By
Jack Turner
MIT Technology Licensing Officer
Patent Protection

Methods and Apparatus for Reducing Timing-skew Errors in Time-interleaved Analog-to-digital Converters

US Patent Pending US 2016-0079994


Applications for this technology are found in communications infrastructure, radar, and electronic surveillance.

Problem Addressed

The clocks of a time-interleaved ADC system are usually generated on-chip by dividing a high-frequency clock. Ideally, each clock should be uniformly spaced in time: however, due to mismatches in layout and clock generator circuits, the clock edges deviate from the ideal case and cuase timing-skew. Timing-skew is a dominant source of error in time-interleaved ADCs causing reduced accuracy and limiting the frequency operating range.


This invention is a system to detect and calibrate timing-skew in time-interleaved ADCs by incorporating a coarse ADC operating at full sampling rate. Since this coarse ADC is not affected by the timing-skew errors, it can be used as a reference signal, eliminating the need for an additional time reference. The method offers simplified computation, which allows it to achieve high resolution and speed at a reduced the footprint and power consumption. Speeds of 1 GHz have been achieved with the current implementation. Achieving 5 Hz samples/sec is envisioned.


  • Achieves high resolutions at high speeds
  • Reduced power consumption