New Structures for GaN Vertical Transistors

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Schematic of the proposed vertical fin power FET and its starting epi-structure.
Professor Tomas Palacios
Department of Electrical Engineering and Computer Science, MIT
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Min Sun
Department of Electrical Engineering and Computer Science, MIT
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Christopher Noble
MIT Technology Licensing Officer - Clean and Renewable Energy
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Structures for Nitride Vertical Transistors

US Patent Pending
High-Performance GaN Vertical Fin Power Transistors on Bulk GaN Substrates
IEEE Electron Device Letters, April 2017, Vol. 38, No. 4, pp. 509-512


Gallium Nitride (GaN) vertical transistors are used in power electronics to achieve high power conversion efficiency.

Problem Addressed

The dominant GaN device architecture today is the lateral High Electron Mobility Transistor (HEMT) heterostructure. However, the lateral GaN HEMT device architecture has two key limitations. First, careful management of electric field profiles in the lateral dimension between contacts is required, particularly in high voltage applications. Substantial gate/drain lateral spacing must be maintained to allow high breakdown voltage, which reduces the effective current density. Second, thermal management is complicated by the fact that all current flow is confined to a relatively thin portion of the device near the top surface. In contrast, a vertical GaN device architecture could overcome these limitations because high electric fields occur between contacts on the bottom and top of the structure in the vertical dimension only.


This new transistor is based on a nano-wire structure. The channel of the transistor is made of a nano-ribbon shaped material, instead of the planar large-area quantum well or two dimensional electron gas (2DEG) typically used in these devices until now. The proposed structure can be implemented on III-N wafers grown both N-face and Ga-face. To achieve high breakdown voltage, special junction termination techniques are used to control and shape the electric field at the edges of the devices. These techniques include field plate, guard rings, bevel edge termination and junction termination extension. The fabricated transistor demonstrated a threshold voltage of 1V and a specific on resistance of 0.36 mΩcm2. By proper electric field engineering, 800 V blocking voltage was achieved at a gate bias of 0 V.


  • Increases break down voltage
  • Increases effective current density