CMOS Readout Circuit Architecture for Large-Format Small-Pixel Photon Counting Focal Plane Arrays Using Geiger-Mode Avalanche Photodiodes

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FIG. 1 is a block diagram of a photon-counting imager that shows the architecture of an individual sensing element, including a counter and an overflow bit in the sensing element according to embodiments of the present invention.FIG. 2A is a block diagram of an overflow bit generated by logic coupled to a counter according to alternative embodiments of the present invention. FIG. 2B is a block diagram of an overflow bit selected by a selector coupled to another counter according to alternative embodiments of the present invention.  FIG. 3 is a block diagram of an avalanche photodiode (APD) reset circuit (quenching circuit not shown).FIG. 4 is a block diagram of a photon-counting imager with a rolling readout system according to embodiments of the present invention.FIG. 5 is a timing diagram showing example overflow bit and counter residue polling periods according to embodiments of the present invention.FIG. 6 is a flow diagram illustrating photon detection and counting according to embodiments of the present invention.FIG. 7 is a flow diagram illustrating alternative photon detection and counting according to an embodiment of the present invention.
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Inventors
Brian Aull
Lincoln Laboratory, MIT
Robert Reich
Lincoln Laboratory, MIT
Matthew Renzi
Lincoln Laboratory, MIT
Daniel Schuette
Lincoln Laboratory, MIT
Managed By
Dave Sossen
MIT Technology Licensing Officer
Patent Protection

CMOS readout architecture and method for photon-counting arrays

US Patent 8,426,797

A complementary metal-oxide-semiconductor (CMOS) readout architecture for photon-counting arrays with a photon-counting detector, a digital counter, and an overflow bit in each of the sensing elements in the array.

Applications

The invention is useful for medical and defense applications (night vision, remote surveillance, adaptive optics and bio-detection); quantum computing; cryptography and information technology; scientific imaging; and imaging for the consumer markets.

Problem Addressed

Current CMOS architecture with one-bit sensing requires a lot of real estate thus limiting the minimum size and spatial resolution of the image. There is a need for photon-counting imagers with low transfer bandwidths, relatively small sensing elements, and high dynamic range.

Technology

The invention is a complementary metal-oxide-semiconductor (CMOS) readout architecture for photon-counting imagers which include an array of sensing elements, each of which includes a photon-counting detector, such as an avalanche photodiode (APD) operating in Geiger mode, a digital counter, and an overflow bit.Typically, the photon-counting detector is a Geiger-mode avalanche photodiode (APD) that emits brief pulses every time it detects a photon. The pulse increments the digital counters, which, in turn, sets the overflow bit once it reaches a given count. A rolling readout system coupled to each sensing element polls the overflow bit, and, if the overflow bit is high, initiates a data transfer from the overflow bit to a frame store.

Advantages

  • CMOS architectures with counters and overflow bits have lower transfer bandwidths, higher dynamic ranges, and dissipate less power when compared to other CMOS architectures.
  • Smaller in size
  • Cheaper to make
  • Better spatial resolution.