Method and Structure for Formation of Crystalline Material on Amorphous Substrates

Technology #14134

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Inventors
Professor Lionel Kimerling
Department of Materials Science and Engineering, MIT
External Link (dmse.mit.edu)
Jurgen Michel
Materials Processing Center, MIT
External Link (photonics.mit.edu)
Jifeng Liu
Materials Processing Center, MIT
External Link (photonics.mit.edu)
Kevin McComber
Department of Materials Science and Engineering, MIT
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Dave Sossen
MIT Technology Licensing Officer
Patent Protection

Confined Lateral Growth of Crystalline Material

US Patent Pending US 2012-0025195

Confined Lateral Growth of Crystalline Material

US Patent Pending
Publications
Silicon Photonics Meets the Foundry
ILP News, June 22nd, 2015

This confined lateral growth method is a technique for growing crystalline material on an amorphous substrate instead of a single crystal substrate. Germanium (Ge) is used as the archetypical crystal but the method could be generalized to other crystals. 

Applications

The process can be applied anywhere single-crystal Ge is desired but epitaxial growth cannot be performed. Potential applications include

  • Electronic-photonic integrated circuits
  • Back-end electronics (e.g. active matrix liquid displays (AMLCDs)
  • Sensors & photovoltaics

Problem Addressed

In a wide range of electronic and optoelectronic applications, there is required an arrangement of one or more semiconducting material layers that are preferably crystalline, herein defined as polycrystalline or monocrystalline. But for many such applications, the device structure employing the material layers cannot accommodate the high temperatures required to produce crystalline layers. For example, in the integration of photonic devices with integrated circuits, it is desired to integrate CMOS electronics with CMOS-compatible photodetectors and modulators operating in the C telecommunications band of 1520 nm-1560 nm. Germanium is particularly well-suited for such optoelectronics devices, but the growth of a crystalline Ge layer on, e.g., a single-crystal Si substrate, conventionally requires a growth temperature above 600° C. by an epitaxial process. Back-end production of Ge optical devices, after CMOS circuitry fabrication, dictates the use of low processing temperatures, e.g., ≦450° C., as well as non-epitaxial growth techniques on an amorphous material surface, for photonic device integration with CMOS circuitry. At such low temperatures, a Ge layer formed by conventional methods is characterized by a small-grain polycrystalline morphology, not the single-crystal morphology that is characteristic of high-temperature epitaxial growth.

It has been suggested to employ the resulting small-grain polycrystalline germanium, rather than single-crystal germanium, for photodetector fabrication in an optoelectronic system, but such devices have been demonstrated to suffer from the high defect density that is characteristic of polycrystalline Ge. The small-grain Ge that is conventionally produced at low temperatures therefore does not enable the required electronics and photonics integration.

Technology

Currently, single crystal Germanium (Ge) must be grown via a chemical vapor deposition or molecular beam epitaxy process on a single crystal substrate in order to be compatible with complementary metal oxide semiconductor (CMOS) technology. This standard procedure limits the processing flexibility for it requires both high temperatures (around 700  ̊C ) and a single crystal substrate.

Crystal growth on amorphous substrates at low temperature (around 400  ̊C) allows for the flexible fabrication of Ge electronic and photonic devices. For example, such a process could be used for the back end fabrication of Ge photonic devices where high temperatures are not needed. The essential aspect of the procedure is that the crystal is initially grown laterally (instead of vertically) from a seed layer and is confined between two insulating layers. This confinement ensures the grown material is single crystalline.

Advantages

  • Single crystal material has a lowed defect density and hence allows for more efficient device performance.
  • Method only requires temperatures of 400  ̊C
  • Process is CMOS compatible