Applications for this technology include:
- Maskless CMOS manufacturing
- CMOS integrated circuits design
- Small batch manufacturing of application specific integrated circuits (ICs) and prototypes
Decreasing CMOS feature sizes have led to prohibitively expensive mask sets for photolithography, which makes low volume production of application specific ICs uncompetitive. Electron beam lithography is a viable alternative, but it is slow - thus lacking sufficient production throughput. The most widely used throughput-augmenting technologies, Reflective Electron Beam Lithography (REBL) and Multiple Aperature Pixel-by-Pixel Enhancement Resolution (MAPPER), have limitations in attainable ultimate resolution.
This technology introduces individually controlled, massively parallel electron sources that can increase throughput in electron beam lithography. While techniques raster a single beam over the wafer or use complex optics to break up a beam into multiple beam-lets, this technology switches silicon field emitter arrays optically to address individual pixels on the wafer. Therefore, the technique allows economically viable means of low volume production.
- Simpler system compared to REBL and MAPPER, avoids complex electron optics
- Robust solution: lower complexity leads to lower potential for equipment failure
- Massively parallel electron beam-lets lead to higher throughput
- Potential resolution is much higher than optical means, and is only limited by the resolution of the resist