Vertical Nitride Semiconductor Device

Technology #16964

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Professor Tomas Palacios
Electrical Engineering and Computer Science
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Yuhao Zhang
Electrical Engineering and Computer Science
Managed By
Christopher Noble
MIT Technology Licensing Officer - Clean and Renewable Energy
Patent Protection

Vertical Nitride Semiconductor Device

US Patent Pending US 2015-0270356
GaN-on-Si Vertical Schottky and p-n Diodes
IEEE Electron Device Letters , June 2014, Volume: 35, Issue: 6, pp. 618 - 620.
High-Performance 500 V Quasi- and Fully-Vertical GaN-on-Si pn Diodes
IEEE Electron Device Letters, Feb. 2017, Volume: 38, Issue: 2, pp. 248-251
Novel Fully Vertical GaN p–n Diode on Si Substrate grown by Metalorganic Chemical Vapor Deposition
Applied Physics Express, Oct. 19, 2016, Volume: 9, Issue: 11,


Nitride semiconductor devices have applications in power electronics, power amplification, digital electronics, radio frequency (RF) switches, and energy delivery systems.

Problem Addressed

The current generation of power converters are silicon based. These devices suffer from the low breakdown voltage and high resistance of silicon, making devices bulky and inefficient. GaN devices have achieved record performance in terms of breakdown voltage and resistance. GaN devices also have the ability to operate at high temperatures, which reduces the requirements for cooling. Current commercial GaN devices are lateral High Electron Mobility Transistors (HEMTs), which are still limited by high cost, lower liability, and integration challenges. Vertical GaN devices have attracted attention due to their potential to sustain high break down voltage combined with a smaller footprint and superior thermal performance. However, using GaN substrate is very costly and previous attempts to transfer GaN devices to foreign substrates have resulted in poor performance.


The invention is a new device structure and fabrication method to produce vertical geometry III-Nitride (e.g. GaN) devices on low-cost substrates (such as silicon) while maintaining excellent device performance. The fabrication process can be generalized within 9 steps, which involve layering III-Nitride on a foreign substrate, creating a trench structure or novel buffer layer structure, and then forming the top and bottom electrodes. This fabrication method provides a general framework for achieving high-current, high-voltage, and high-efficiency devices that can easily be integrated with existing chip technologies. The exact deposition and etching methods will vary based on the particular application, but this fabrication allows a truly vertical instead of quasi-vertical device structure through the use of a semiconductor buffer layer.


  • Lowers device cost
  • Increases device efficiency, current, and breakdown voltage 
  • Generalizable to many different types of devices